These VLSI interview questions and answers build a beginner practice sequence: identify logic and state, explain a storage element, check a timing path, and distinguish a functional model from a physical implementation. The questions and worked exercise are independently written for this guide. They are not a company's actual question list, an assessment-frequency ranking, or a promise about recruitment outcomes.
Start with the assumptions. A correct answer to a small binary exercise can become incomplete when the interviewer adds an asynchronous input, a different clock, or an unspecified initial state. Say what your model covers before doing the calculation.
1. What separates combinational and sequential logic?
Combinational logic computes a settled output from current inputs. Sequential logic retains state, so its behavior can depend on earlier events. A clock coordinates updates in a synchronous design; sequential logic is a broader category than edge-triggered circuits.
For practice, describe a rule that sounds like it needs memory, then identify the missing state. “Output one when the two present inputs differ” needs their current values. “Output one when the input has changed since the previous sample” also needs a previous sample. Explain the difference before drawing either circuit.
2. How does a latch differ from a flip-flop?
In this guide, a D latch is level-sensitive: it follows D while enabled and retains its value when disabled. An edge-triggered D flip-flop samples around its selected clock edge. Both store state. Terminology can vary; this guide uses the edge-triggered meaning.
A useful follow-up is to ask which event the question specifies. Is the storage element enabled during a level, or does the question identify a rising edge? Sketch that event first. Do not silently substitute one device for the other just because both diagrams have D and Q labels.
3. What are setup time, hold time, and clock-to-Q delay?
Setup and hold describe required data stability before and after a sampling event. Clock-to-Q describes the output delay following a clock event. For a simplified same-clock, single-cycle register path with zero skew and uncertainty:
T >= tCQ,max
+ tlogic,max + tsetup
tCQ,min + tlogic,min
>= thold
Include modeled routing. Setup uses slow bounds; hold uses fast bounds. These teaching equations have a limited scope. MIT's sequential-building-blocks lecture supports the distinctions and simplified constraints in Questions 1–3.
Before calculating, label the launching register, receiving register, selected edges, and units. Keep maximum and minimum values in separate lines.
4. Can a path pass setup and fail hold?
Yes. Calculate the two checks independently. The exercise below intentionally gives different answers, so a positive result on one line cannot stand in for the other.
Show the arrival and required budgets. If minimum-delay information is missing, name that gap rather than inventing a value.
5. What is the difference between simulation and synthesis?
Simulation evaluates a model for supplied stimuli. Synthesis transforms supported descriptions into a circuit representation. Passing chosen simulations does not establish every input case, synthesis compatibility, or physical timing. A clocked description can represent logic feeding registers; it is not a software instruction executed inside the chip.
When reviewing an answer, separate its evidence. “I checked all eight binary input combinations” is a precise claim. “The circuit works” is broader and needs a defined meaning. List the checks actually performed before discussing what remains to be verified.
6. What does a nonblocking assignment do in RTL?
A nonblocking assignment evaluates its right-hand expression when executed and defers the destination update. In a simple clocked state update, this lets expressions use existing register values before the updates take effect. It does not mean an extra clock cycle or an instantaneous physical change.
The Yosys synthesis primer supports the simulation, synthesis, and assignment distinctions in Questions 5–6.
7. Should every assignment use the same operator?
For beginner RTL, a useful convention is nonblocking assignments for clocked state updates and blocking assignments for combinational calculations. The operator alone does not determine storage, and a coding convention is not a universal legality rule. Verilator's assignment warnings explain the convention and its race-avoidance purpose.
If asked to repair code, first write the intended behavior in words. Then compare the code's behavior with that intention. Changing punctuation before establishing the intended update can hide the real question.
8. What does a synchronizer solve, and what does it leave unresolved?
Metastability is an analog settling phenomenon associated with unfavorable sampling timing. A violation can cause it; it does not guarantee it. A destination-domain synchronizer chain provides settling time and reduces downstream failure probability. Two stages do not eliminate the risk or suit every clock rate and device.
A simple level synchronizer may miss a short pulse. Synchronizing bus bits independently can produce an incoherent word. Coherent data or reliable events may need a properly designed handshake or asynchronous FIFO. A digital X is not an analog metastability simulation. Ran Ginosar's university-hosted tutorial supports these limitations.
In a practice answer, identify whether the transfer is a persistent level, an event, or a data word. Explain what the receiver must observe. “Add two flip-flops” is incomplete if it does not address that requirement.
9. Worked exercise: derive and register enabled parity
Design a one-bit input D that is one only when en is one and a differs from b. Capture D in an edge-triggered register.
The contract permits binary inputs only. Here, en gates the parity value; it is not a register clock enable. When en is zero, the next valid capture writes zero rather than preserving the previous Q. No reset behavior is specified, and Q before its first valid capture is outside this exercise's contract.
An independently derived expression is:
D = en & (a ^ b)
Read & as bitwise AND and ^ as bitwise XOR for these one-bit inputs. The compact table lists inputs in the order en,a,b:
| Inputs | D / next Q |
|---|---|
| 0,0,0 | 0 |
| 0,0,1 | 0 |
| 0,1,0 | 0 |
| 0,1,1 | 0 |
| 1,0,0 | 0 |
| 1,0,1 | 1 |
| 1,1,0 | 1 |
| 1,1,1 | 0 |
To check your reasoning, take 1,0,1: the inputs differ and enable is asserted, so D is one. Now change only enable to zero: the answer becomes zero. Finally test 1,1,1: enable is asserted, but the inputs do not differ.
This table describes settled binary values and the value captured when timing is satisfied. It does not describe transition hazards, unknown values, or an analog waveform.
10. Worked exercise: check both timing bounds
Extend the exercise with three launch registers supplying en, a, and b, and one destination register capturing D. Assume one rising-edge clock and a single-cycle transfer, with zero clock skew and uncertainty. The combined path bounds below already include relevant logic and routing.
Every figure is invented for this exercise. None is a cell-library measurement or a timing-tool result.
| Parameter | Value in ns |
|---|---|
| Clock period | 1.00 |
| Clock-to-Q max / min | 0.12 / 0.04 |
| Logic + routing max / min | 0.58 / 0.02 |
| Setup / hold | 0.08 / 0.09 |
Calculate the setup budget:
Minimum modeled period
= 0.12 + 0.58 + 0.08
= 0.78 ns
Setup slack at 1.00 ns
= 1.00 - 0.78
= +0.22 ns
Then calculate hold separately:
Hold slack
= 0.04 + 0.02 - 0.09
= -0.03 ns
The supplied setup condition passes; the supplied hold condition fails. Reducing only the period to 0.80 ns changes setup slack to +0.02 ns while leaving this hold calculation at −0.03 ns. Increasing only the period likewise leaves the modeled same-edge hold failure unresolved.
As an arithmetic follow-up, suppose an added buffer contributes 0.04 ns minimum delay and 0.07 ns maximum delay. Hold slack becomes +0.01 ns; setup slack becomes +0.15 ns. This hypothetical change passes both supplied inequalities. It is not a recommendation for a particular buffer or a guarantee about an implemented circuit.
The model excludes latch transparency, time borrowing, multiple clocks, clock uncertainty, and special timing constraints. Its positive setup and hold values are supplied parameters, not a claim that every storage element has positive values.
11. What was actually checked in this exercise?
All eight binary rows were executed in Python, comparing the expression with the independently written predicate “enable is one and the inputs differ.” The complete result vector was also checked against the table. Exact decimal arithmetic checked the period, both slack calculations, buffer follow-up, and alternate period; all passed.
No HDL simulation, synthesis, physical implementation, or static timing analysis was performed. That boundary matters: the executed checks establish the Boolean and numerical answers above, not a hardware signoff result.
12. How should I practise answering these questions?
Use a short, repeatable record:
- Write the permitted inputs, initial-state assumptions, and required result.
- Answer in one direct sentence, then explain the reason.
- Draw the relevant state, path, or sampling event.
- Work one ordinary example and one boundary case.
- Check the result independently and record what you actually ran.
- Change one assumption and explain which conclusion needs revisiting.
For the parity exercise, try changing “write zero when disabled” to “retain Q when disabled.” Your original table answers the first requirement, so it cannot simply be reused as the complete answer to the second. For timing, remove the minimum-delay figure and identify which check is now missing evidence. For a crossing, replace a persistent level with a brief event and explain the new delivery requirement.
Record the mistaken assumption, the smallest example that exposed it, and the revised answer. Explained corrections are more useful than a list of question titles.
Frequently asked questions
Must I memorise the numerical answers?
No. Recalculate them from the supplied values and assumptions. Memorising +0.22 ns does not help when a question changes the period or one delay bound.
Can I use these as actual company questions?
They are original practice material. Follow an employer's own instructions for its assessment format, permitted tools, and scope. This guide makes no claim about its question bank.
What should I do when the question is underspecified?
Name the missing information and give a conditional answer. For example: “With the supplied maximum delays, this setup calculation passes; I still need minimum delays for the separate hold check.” That preserves a useful result without pretending the evidence is complete.